1. Technical Field
This invention relates to the field of transistor gate conductor structures in semiconductor devices. More specifically, the invention relates to a method for forming a trimmed gate in a transistor and the apparatus formed thereby.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced. The push for ever increasing device densities is particularly strong in complimentary metal-oxide semiconductor (CMOS) technologies, such as in the design and fabrication of field effect transistors (FETs). FETs are used in almost all types of integrated circuit design (i.e., microprocessors, memory, etc.)
One feature that increases device density is a xe2x80x9ctrimmedxe2x80x9d gate conductor. In general, it is desirable to make gate conductors smaller in semiconductor devices so the associated FETs are faster and operate at lower power. Typically, lithographic methods are used to define gate conductors and then etch processes trim the lithographically formed structure to create sub-lithographic dimensions. However, etch processes are limited in the magnitude of material that can be trimmed from a gate conductor while still maintaining the proper scale of the device. That is, as more of the gate conductor is trimmed by etching, the risk of producing a distorted or defective gate conductor increase. Since sidewall spacers, contacts to diffusion areas, contacts to gates, etc. are typically formed after trimming, distorted gates can lead to misalignment of device components and failure of the device. Accordingly, additional methods are needed that may be combined with current methods or used alone to further trim gate conductors or trim gate conductors by a different technique than presently available.
Another problem with the current fabrication of FETs is that methods for device compensation are in need of improvement. Device compensation is where the relative size (i.e., the gate width to length ratio) of some devices is changed. There are several reasons why device compensation might be required. For example, the speed of CMOS FETs is critically dependant on the width to length ratio of a gate on a given device. In many cases, circuit design requires individual compensation of n-channel and p-channel performance to achieve proper timing between devices. This requires the ability to selectively compensate the width to length ratio of n-channel and p-channel devices. For example, the timing of logic circuitry critically depends on accurate speed control on n-channel as well as p-channel devices, and this may require shortening the length of all n-channel devices by one amount and shortening the length of all p-channel devices by another amount. Thus, as CMOS processes mature, the ability to selectively adjust the physical gate length of n-channel and p-channel devices to compensate for process and device-physics induced speed differences is needed.
Therefore, there existed a need to provide an improved method for trimming gate conductors and an improved method of selective device compensation.
According to the present invention, a method is provided for forming a trimmed gate in a transistor comprising the steps of forming a polysilicon portion of a gate conductor on a substrate having a semiconductor portion and trimming the polysilicon portion by a film growth method chosen from among selective surface oxidation and selective surface nitridation. By way of example, the trimming step may selectively compensate n-channel and p-channel devices. Also, the trimming film may optionally be removed by a method chosen from among anisotropic and isotropic etching. Further, gate conductor spacers may be formed by anisotropic etching of the grown film. Also according to the present invention, a transistor is provided comprising a trimmed polysilicon portion of a gate conductor, wherein the trimming occurred by a film growth method chosen from among selective surface oxidation and selective surface nitridation.